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rev. 1.4 1/06 copyright ? 2006 by silicon laboratories si4136/si4126 si4136/si4126 ism rf s ynthesizer w ith i ntegrated vco s f or w ireless c ommunications features applications description the si4136 is a monolithic integrated circuit that performs both if and rf synthesis for wireless communicati ons applications. the si4136 includes three vcos, loop filters, referenc e and vco dividers, and phase detectors. divider and powerdown settings are programmable through a three-wire serial interface. functional block diagram dual-band rf synthesizers rf1: 2300 mhz to 2500 mhz rf2: 2025 mhz to 2300 mhz if synthesizer 62.5 mhz to 1000 mhz integrated vcos, loop filters, varactors, and resonators minimal external components required low phase noise 5 a standby current 25.7 ma typical supply current 2.7 v to 3.6 v operation packages: 24-pin tssop, 28-lead qfn lead-free/rohs-compliant options available ism and mmds band communications wireless lan and wan dual-band communications ifout ifla iflb rfout xin pwdn sdata sclk sen if rf2 rf1 auxout phase detect phase detect 2 2 ifdiv phase detect test mux 22-bit data register serial interface power down control reference amplifier r rf1 r rf2 r if n rf1 n rf2 n if 1/2 patents pending ordering information: see page 29. pin assignments si4136-bt/gt si4136-bm/gm sclk sdata gnd gnd nc gnd nc gnd gnd gnd rfout vddr sen vddi ifout gnd iflb ifla gnd vddd gnd xin pwdn auxout 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 sclk sdata gnd gnd nc nc gnd gnd rfout vddr sen vddi ifout gnd iflb ifla gnd vddd gnd xin pwdn auxout 21 20 19 18 17 16 15 8 9 10 11 12 13 14 28 27 26 25 24 23 22 1 2 3 4 5 6 7 gnd gnd gnd gnd gnd gnd gnd
si4136/si4126 2 rev. 1.4
si4136/si4126 rev. 1.4 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.1. serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.2. setting the if vco cent er frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3. self-tuning algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4. output frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5. pll loop dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6. rf and if outputs (rfout and ifout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.7. reference frequency amplif ier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.8. powerdown modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.9. auxiliary output (auxout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4. pin descriptions: si4136-bt/gt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. pin descriptions: si4136-bm/gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7. si4136 derivative devic es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 0 8. package outline: si 4136-bt/gt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9. package outline: si4136- bm/gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
si4136/si4126 4 rev. 1.4 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit ambient temperature t a ?40 25 85 c supply voltage v dd 2.7 3.0 3.6 v supply voltages difference v ? (v ddr ? v ddd ), (v ddi ? v ddd ) ?0.3 ? 0.3 v note: all minimum and maximum specifications are guaranteed an d apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25c unless otherwise stated. table 2. absolute maximum ratings 1,2 parameter symbol value unit dc supply voltage v dd ?0.5 to 4.0 v input current 3 i in 10 ma input voltage 3 v in ?0.3 to v dd +0.3 v storage temperature range t stg ?55 to 150 o c notes: 1. permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. this device is a high performance rf integrated circ uit with an esd rating of < 2 kv. handling and assembly of this device should only be done at esd-protected workstations. 3. for signals sclk, sdata, sen , pwdn , and xin.
si4136/si4126 rev. 1.4 5 table 3. dc characteristics (v dd = 2.7 to 3.6 v, t a = ?40 to 85 c) parameter symbol test condition min typ max unit total supply current 1 rf1 and if operating ? 25.7 31 ma rf1 mode supply current 1 ?15.719ma rf2 mode supply current 1 ?1518ma if mode supply current 1 ?1012ma standby current pwdn = 0 ? 1 ? a high level input voltage 2 v ih 0.7 v dd ??v low level input voltage 2 v il ? ? 0.3 v dd v high level input current 2 i ih v ih = 3.6 v, v dd = 3.6 v ?10 ? 10 a low level input current 2 i il v il = 0 v, v dd = 3.6 v ?10 ? 10 a high level output voltage 3 v oh i oh = ?500 a v dd ?0.4 ? ? v low level output voltage 3 v ol i oh = 500 a ? ? 0.4 v notes: 1. rf1 = 2.4 ghz, rf2 = 2.1 ghz, ifout = 800 mhz, lpwr = 0. 2. for signals sclk, sdata, sen , and pwdn . 3. for signal auxout.
si4136/si4126 6 rev. 1.4 figure 1. sclk timing diagram table 4. serial interface timing (v dd = 2.7 to 3.6 v, t a = ?40 to 85 c) parameter 1 symbol test condition min typ max unit sclk cycle time t clk figure 1 40 ? ? ns sclk rise time t r figure 1 ? ? 50 ns sclk fall time t f figure 1 ? ? 50 ns sclk high time t h figure 1 10 ? ? ns sclk low time t l figure 1 10 ? ? ns sdata setup time to sclk 2 t su figure 2 5 ? ? ns sdata hold time from sclk 2 t hold figure 2 0 ? ? ns sen to sclk delay time 2 t en1 figure 2 10 ? ? ns sclk to sen delay time 2 t en2 figure 2 12 ? ? ns sen to sclk delay time 2 t en3 figure 2 12 ? ? ns sen pulse width t w figure 2 10 ? ? ns notes: 1. all timing is referenced to the 50% level of the waveform, unless otherwise noted. 2. timing is not referenced to 50% level of the waveform. see figure 2. sclk 80% 50% 20% t r t f t h t l t clk
si4136/si4126 rev. 1.4 7 figure 2. serial interface timing diagram figure 3. serial word format a a d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 3 a 2 a 1 fi rst bi t clocked in l ast b i t clocked i n address field a 0 data field
si4136/si4126 8 rev. 1.4 table 5. rf and if synthesizer characteristics (v dd = 2.7 to 3.6 v, t a = ?40 to 85 c) parameter 1 symbol test condition min typ max unit xin input frequency f ref xindiv2 = 0 2 ? 25 mhz xin input frequency f ref xindiv2 = 1 25 ? 50 mhz reference amplif ier sensitivity v ref 0.5 ? v dd +0.3 v v pp phase detector update frequency f f = f ref /r for xindiv2 = 0 f = f ref /2r for xindiv2 = 1 0.010 ? 1.0 mhz rf1 vco tuning range 2 2300 ? 2500 mhz rf2 vco tuning range 2 2025 ? 2300 mhz if vco center frequency range f cen 526 ? 952 mhz ifout tuning range from f cen with ifdiv 62.5 ? 1000 mhz ifout vco tuning range from f cen note: l 10% ?5 ? 5 % rf1 vco pushing open loop ? 0.75 ? mhz/v rf2 vco pushing ? 0.65 ? mhz/v if vco pushing ? 0.10 ? mhz/v rf1 vco pulling vswr = 2:1, all phases, open loop ? 0.250 ? mhz p-p rf2 vco pulling ? 0.100 ? mhz p-p if vco pulling ? 0.025 ? mhz p-p rf1 phase noise 1 mhz offset ? ?130 ? dbc/hz rf1 integrated phase error 100 hz to 100 khz ? 1.2 ? degrees rms rf2 phase noise 1 mhz offset ? ?131 ? dbc/hz rf2 integrated phase error 100 hz to 100 khz ? 1.0 ? degrees rms if phase noise at 800 mhz 100 khz offset ? ?104 ? dbc/hz if integrated phase error 100 hz to 100 khz ? 0.4 ? degrees rms notes: 1. f (rf) = 1 mhz, f (if) = 1 mhz, rf1 = 2.4 ghz, rf2 = 2.1 ghz, if out = 800 mhz, lpwr = 0, for all parameters unless otherwise noted. 2. rf vco tuning range limits are fixed by inductance of internally bonded wires. 3. from powerup request (pwdn or sen during a write of 1 to bits pdib and pdrb in register 2) to rf and if synthesizers ready (settled to within 0.1 ppm frequency error). 4. from powerdown request (pwdn , or sen during a write of 0 to bits pdib and p drb in register 2) to supply current equal to i pwdn .
si4136/si4126 rev. 1.4 9 rf1 harmonic suppression second harmonic ? ?28 ?20 dbc rf2 harmonic suppression ? ?23 ?20 dbc if harmonic suppression ? ?26 ?20 dbc rfout power level z l = 50 ?, rf1 active ?7 ?3.5 ?0.5 dbm rfout power level z l = 50 ?, rf2 active ?7 ?3.5 ?0.5 dbm ifout power level z l = 50 ? ?7 ?4 0 dbm rf1 output reference spurs offset = 1 mhz ? ?63 ? dbc offset = 2 mhz ? ?68 ? dbc offset = 3 mhz ? ?70 ? dbc rf2 output reference spurs offset = 1 mhz ? ?63 ? dbc offset = 2 mhz ? ?68 ? dbc offset = 3 mhz ? ?70 ? dbc powerup request to synthesizer ready 3 time t pup figures 4, 5 f > 500 khz ? 80 100 s powerup request to synthesizer ready 3 time t pup figures 4, 5 f 500 khz ?40/f 50/f powerdown request to synthesizer off 4 time t pdn figures 4, 5 ? ? 100 ns table 5. rf and if synthesizer characteristics (continued) (v dd = 2.7 to 3.6 v, t a = ?40 to 85 c) parameter 1 symbol test condition min typ max unit notes: 1. f (rf) = 1 mhz, f (if) = 1 mhz, rf1 = 2.4 ghz, rf2 = 2.1 ghz, if out = 800 mhz, lpwr = 0, for all parameters unless otherwise noted. 2. rf vco tuning range limits are fixed by inductance of internally bonded wires. 3. from powerup request (pwdn or sen during a write of 1 to bits pdib and pdrb in register 2) to rf and if synthesizers ready (settled to within 0.1 ppm frequency error). 4. from powerdown request (pwdn , or sen during a write of 0 to bits pdib and p drb in register 2) to supply current equal to i pwdn .
si4136/si4126 10 rev. 1.4 figure 4. software power management timing diagram figure 5. hardware power management timing diagram pdib = 0 pdrb = 0 pdib = 1 pdrb = 1 t pup t pdn i t i pwdn sen sdata rf synthesizers settled to within 0.1 ppm frequency error. t pup t pdn i t i pwdn pwdn rf synthesizers settled to within 0.1 ppm frequency error.
si4136/si4126 rev. 1.4 11 figure 6. typical transient response rf1 at 2.4 ghz with 1 mhz phase detector update frequency
si4136/si4126 12 rev. 1.4 figure 7. typical rf1 phase noise at 2.4 ghz with 1 mhz phase detector update frequency figure 8. typical rf1 spurious response at 2.4 ghz with 1 mhz phase detector update frequency typical rf1 phase noise at 2.4 ghz -140 -130 -120 -110 -100 -90 -80 -70 -60 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 offset frequency (hz) phase noise (dbc/hz)
si4136/si4126 rev. 1.4 13 s figure 9. typical rf2 phase noise at 2.1 ghz with 1 mhz phase detector update frequency figure 10. typical rf2 spurious response at 2.1 ghz with 1 mhz phase detector update frequency typical rf2 phase noise at 2.1 ghz -140 -130 -120 -110 -100 -90 -80 -70 -60 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 offset frequency (hz) phase noise (dbc/hz)
si4136/si4126 14 rev. 1.4 figure 11. typical if phase noise at 800 mhz with 1 mhz phase detector update frequency figure 12. if spurious response at 800 mhz with 1 mhz phase detector update frequency typical if phase noise at 800 mhz -140 -130 -120 -110 -100 -90 -80 -70 -60 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 offset frequency (hz) phase noise (dbc/hz)
si4136/si4126 rev. 1.4 15 figure 13. typical applicat ion circuit: si4136-bt/gt sclk sdata gnd gnd nc gnd nc gnd gnd gnd rfout vddr sen vddi ifout gnd iflb ifla gnd vddd gnd xin pwdn auxout 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 si4136 rfout 560 pf printed trace inductor or chip inductor ifout 560 pf l match auxout external clock 560 pf from system controller 0.022 f v dd 0.022 f 0.022 f pdwnb v dd v dd 30 ? ? *add 30 ? series resistor if using if output divide values 2, 4, or 8 and f cen < 600 mhz.
si4136/si4126 16 rev. 1.4 2. functional description the si4136 is a monolithi c integrated circuit that performs if and dual-band rf synthesis for many wireless communications applications. this integrated circuit (ic), along with a mi nimum number of external components, is all that is necessary to implement the frequency synthesis function in applications like w-lan using the ieee 802.11 standard. the si4136 has three complete phase-locked loops (plls), with integrated vo ltage-controll ed oscillators (vcos). the low phase noise of the vcos makes the si4136 suitable for use in demanding wireless communications applications. also integrated are phase detectors, loop filters, and reference and output frequency dividers. the ic is programmed through a three-wire serial interface. two plls are provided for rf synthesis. these rf plls are multiplexed so that only one pll is active at a given time (as determined by the setting of an internal register). the active pll is the last one written. the center frequency of the vco in each pll is set by the internal bond wire inductance within the package. inaccuracies in these inductances are compensated for by the self-tuning algorithm. the algorithm is run following power-up or fo llowing a change in the programmed output frequency. the rf plls contain a divide -by-2 circuit before the n- divider. as a result, the phase detector frequency (f ) is equal to half the desired channel spacing. for example, for a 200 khz channel spacing, f would equal 100 khz. the if pll does not contai n the divide-by-2 circuit before the n-divider . in this case, f is equal to the desired channel spacing. each rf vco is optimized for a particular frequency range. the rf1 vco is optimized to operate from 2.3 ghz to 2.5 ghz, while the rf2 vco is optimized to operate between 2.025 ghz and 2.3 ghz. one pll is provided for if synthesis. the center frequency of this circuit?s vco is set by an external inductance. the pll can adjust the if output frequency by 5% of the vco center frequency. inaccuracies in the value of the external inductance are compensated for by the si4136?s proprietary self-tuning algorithm. this algorithm is initiated ea ch time the pll is powered- up (by either the pwdn pin or by software) and/or each time a new output frequency is programmed. the if vco can have its center frequency set as low as 526 mhz and as high as 952 m hz. an if output divider is provided to divide down the if output frequencies, if needed. the divider is programmable, capable of dividing by 1, 2, 4, or 8. in order to accommodate designs running at xin frequencies greater than 25 mhz, the si4136 includes a programmable divide-by-2 option (xindiv2 in register 0, d6) on the xin input. by enabling this option, the si4136 can accept a range of tcxo frequencies from 25 mhz to 50 mhz. this feature makes the si4136 ideal for w-lan radio designs operating at an xin of 44 mhz. the unique pll architecture used in the si4136 produces settling (lock) ti mes that are comparable in speed to fractional-n architectures without suffering the high phase noise or spurious modulation effects often associated with those designs. 2.1. serial interface a timing diagram for the serial interface is shown in figure 2 on page 7. figure 3 on page 7 shows the format of the serial word. the si4136 is programmed serially with 22-bit words comprised of 18-bit data fields and 4-bit address fields. when the serial interface is enabled (i.e., when sen is low) data and address bits on the sdata pin are clocked into an internal shift register on the rising edge of sclk. data in the shift register is then transferred on the rising edge of sen into the internal data register addressed in the address field. the serial interface is disabled when sen is high. table 11 on page 21 summarizes the data register functions and addresses. it is not necessary (although it is permissible) to clock into the internal shift register any leading bits that are ?don?t cares.? 2.2. setting the if vco center frequencies the if pll can adjust its output frequency 5% from the center frequency as esta blished by the value of an external inductance connected to the vco. the rf1 and rf2 plls have fixed operating ranges due to the inductance set by the internal bond wires. each center frequency is established by the value of the total inductance (internal and/or external) connected to the respective vco. manufacturing tolerance of 10% for the external inductor is acceptable for the if vco. the si4136 will compensate for ina ccuracies by executing a self-tuning algorithm fo llowing pll power-up or following a change in the programmed output frequency. because the total tank inductance is in the low nh range, the inductance of the package needs to be considered in determining the correct external inductance. the total inductance (l tot ) presented to the if vco is the sum of the external inductance (l ext ) and the package inductance (l pkg ). the if vco has a nominal capacitance (c nom ) in parallel with the total inductance, and the center frequency is as follows:
si4136/si4126 rev. 1.4 17 table 6 summarizes the characteristics of the if vco. figure 14. example of if external inductor as a design example, suppose synthesizing frequencies in a 30 mhz band between 735 mhz and 765 mhz is desired. the center frequency should be defined as midway between the two extremes, or 750 mhz. the pll will be able to adjust the vco output frequency 5% of the center frequency, or 37.5 mhz of 750 mhz (i.e., from approximately 713 mhz to 788 mhz). the if vco has a c nom of 6.5 pf, and a 6.9 nh inductance (correct to two digits) in parallel with this capacitance will yield t he desired cent er frequency. an external inductance of 4.8 nh should be connected between ifla and iflb, as shown in figure 14. this, in addition to 2.1 nh of pa ckage inductance, will present the correct total inductance to the vco. in manufacturing, the external inductance can vary 10% of its nominal value and the si4136 will correct for the variation with the self-tuning algorithm. for more information on designing the external trace inductor, please refer to application note 31. 2.3. self-tuning algorithm the self-tuning algorithm is initiated immediately following power-up of a pll or, if the pll is already powered, following a change in its programmed output frequency. this algorithm attempts to tune the vco so that its free-running frequency is near the desired output frequency. in so doing, the algorithm will compensate for manufacturing tolerance errors in the value of the external inductance connected to the if vco. it will also reduce the frequency error for which the pll must correct to get the precise desired output frequency. the self-tuning algorithm will le ave the vco oscillating at a frequency in error by somewhat less than 1% of the desired output frequency. after self-tuning, the pll c ontrols the vco oscillation frequency. the pll will comp lete frequency locking, eliminating any remaining frequency error. thereafter, it will maintain frequency-lock, compensating for effects caused by temperature and supply voltage variations. the si4136?s self-tuning al gorithm will compensate for component value errors at any temperature within the specified temperatur e range. however, the ability of the pll to compensate for drift in component values that occur after self-tuning is limited. for external inductances with temperature coefficients around 150 ppm/c, the pll will be able to maintain lock for changes in temperature of approximately 30c. applications where the pll is regularly powered-down or the frequency is periodically reprogrammed minimize or eliminate the potential effects of temperature drift because the vco is re-tuned in either case. in applications where the ambient temperature can drift substantially after self-tun ing, it may be necessary to monitor the lock-detect bar (ldetb) signal on the auxout pin to determine whether a pll is about to run out of locking capability. (see ?2.9. au xiliary output (auxout)? for how to select ldetb.) the ldetb signal will be low after self-t uning has comp leted but will rise when either the if or rf pll nears the limit of its compensation range. (ldetb will also be high when either pll is executing the self-tuning algorithm.) the output frequency will still be locked when ldetb goes high, but the pll will eventually lose lock if the temperature continues to drift in the same direction. therefore, if ldetb goes high both the if and rf plls should promptly be re-tuned by initiating th e self-tuning algorithm. 2.4. output frequencies the if and rf output frequencies are set by programming the r- and n-divider registers. each pll has its own r and n registers so that each can be table 6. si4136-bt/gt vco characteristics vco fcen range (mhz) cnom (pf) lpkg (nh) lext range (nh) min max min max if 526 952 6.5 2.1 2.2 12.0 f cen 1 2 l tot c nom ? --------------------------------------------- 1 2 l pkg l ext + () c nom ? ---------------------------------------------------------------------- == si4136 l pkg 2 l pkg 2 l ext iflb ifla
si4136/si4126 18 rev. 1.4 programmed independently. programming either the r- or n-divider register for rf1 or rf2 automatically selects the associated output. when xindiv2 = 0, the reference frequency on the xin pin is divided by r and this signal is the input to the pll?s phase detector. the other input to the phase detector is the pll?s vco output frequency divided by 2n for the rf plls or n for the if pll. after an initial transient equation 1. f out = (2n/r) f ref (for the rf plls) equation 2. f out = (n/r) f ref (for the if pll). the integers r are set by programming the rf1 r- divider register (register 6), the rf2 r-divider register (register 7) and the if r-divider register (register 8). the integers n are set by programming the rf1 n- divider register (register 3) , the rf2 n-divider register (register 4), and the if n-div ider register (register 5). if the optional divide-by-2 circuit on the xin pin is enabled (xindiv2 = 1) then after an initial transient f out = (n/r) f ref (for the rf plls) f out = (n/2r) f ref (for the if pll). each n-divider is implemented as a conventional high speed divider. that is, it consists of a dual-modulus prescaler, a swallow counter, and a lower speed synchronous counter. however, the control of these sub-circuits is handled automatically. only the appropriate n value should be programmed. 2.5. pll loop dynamics the transient response for each pll is determined by its phase detector update rate f (equal to f ref /r) and the phase detector gain programmed for each rf1, rf2, or if synthesizer. (see register 1.) four different settings for the phase detector gain are available for each pll. the highest gain is programmed by setting the two phase detector gain bits to 00, and the lowest by setting the bits to 11. the values of the available gains, relative to the highest gain, are listed in table 7. in general, a higher phas e detector gain will decrease in-band phase noise and increase the speed of the pll transient until the point at which stability begins to be compromised. the optimal gain depends on n. table 8 lists recommended settings for different values of n. the vco gain and loop filter characteristics are not programmable. the settling time for each pll is directly proportional to its phase detector update period t (t equals 1/f ). during the first 13 update periods the si4136 executes the self-tuning algorithm. thereafter the pll controls the output frequency. because of the unique architecture of the si4136 plls, the time required to settle the output frequency to 0.1 ppm error is only about 25 update periods. thus, the total time after power-up or a change in programmed frequency until the synthesized frequency is well settled?including time for self-tuning?is around 40 update periods. note: this settling time analysis holds for f 500 khz . for f > 500 khz , the settling time can be a maximum of 100 s as specified in table 5. 2.6. rf and if outputs (rfout and ifout) the rfout and ifout pins are driven by amplifiers that buffer the rf vcos and if vco, respectively. the rf output amplifier receives its input from either the rf1 or rf2 vco, depending upon which r- or n- divider register was last written. for example, programming the n-divider register for rf1 automatically selects the rf1 vco output. figure 13 on page 15 shows an application diagram for the si4136. the rf output si gnal must be ac coupled to its load through a capacitor. the ifout pin must also be ac coupled to its load through a capacitor. the if output level is dependent upon the load. figure 17 displays the output level versus load resistance. for resistive loads greater than 500 ? the output level saturates and the bias currents in the if output amplifier are hi gher than they need to be. the lpwr bit in the main configuration register table 7. gain values (register 1) k p bits relative p.d. gain 00 1 01 1/2 10 1/4 11 1/8 table 8. optimal k p settings n rf1 k p1 <1:0> rf2 k p2 <1:0> if k pi <1:0> 2047 00 00 00 2048 to 4095 00 01 01 4096 to 8191 01 10 10 8192 to 16383 10 11 11 16384 11 11 11
si4136/si4126 rev. 1.4 19 (register 0) can be set to 1 to reduce the bias currents and therefore reduce the po wer dissipated by the if amplifier. for loads less than 500 ?, lpwr should be set to 0 to maximize the output level. for if frequencies greater than 500 mhz, a matching network is required in order to drive a 50 ? load. see figure 15 below. the value of l match can be determined by table 9. typical values range between 8 nh and 40 nh. figure 15. if frequencies > 500 mhz for frequencies less than 500 mhz, the if output buffer can directly drive a 200 ? resistive load or higher. for resistive loads greater than 500 ? (f < 500 mhz) the lpwr bit can be set to reduce the power consumed by the if output buffer. see figure 16 below. figure 16. if frequencies < 500 mhz figure 17. typical if output voltage vs. load resistance at 550 mhz 2.7. reference frequency amplifier the si4136 provides a reference frequency amplifier. if the driving signal has cmos levels, it can be connected directly to the xin pin. otherwise, the reference frequency signal should be ac coupled to the xin pin through a 560 pf capacitor. 2.8. powerdown modes table 10 summarizes the powerdown functionality. the si4136 can be powered down by taking the pwdn pin low or by setting bits in the powerdown register (register 2). when the pwdn pin is low, the si4136 will be powered down regardless of the powerdown register settings. when the pwdn pin is high, power management is under control of the powerdown register bits. the if and rf sections of the si4136 circuitry can be individually powered down by setting the powerdown register bits pdib and pdrb low. the reference frequency amplifier will also be powered up if either the pdrb and pdib bits are high. also, setting the autopdb bit to 1 in the main configuration register (register 0) is equivalent to setting both bits in the powerdown register to 1. the serial interface remains available and can be written in all po wer-down modes. 2.9. auxiliary output (auxout) the signal appearing on auxout is selected by setting the auxsel bits in the main configuration register (register 0). the ldetb signal can be selected by setting the auxsel bits to 011. this signal can be used to indicate that the if or rf pll is about to lose lock due to excessive ambient temperature drift and should be re- tuned. table 9. l match values frequency l match 500?600 mhz 40 nh 600?800 mhz 27 nh 800?1 ghz 18 nh ifout l match >500 pf 50 ? ifout >500 pf >200 ? 0 50 100 150 200 250 300 350 400 450 0 200 400 600 800 1000 1200 load resistance ( ? ) output voltage (mvrms) lpwr=0 lpwr=1
si4136/si4126 20 rev. 1.4 table 10. powerdown configuration pwdn pin autopdb pdib pdrb if circuitry rf circuitry pwdn = 0 x x x off off pwdn = 1 000offoff 001offon 010onoff 011onon 1xxonon note: x = don?t care.
si4136/si4126 rev. 1.4 21 3. control registers note: registers 9?15 are reserved. writes to these registers may result in unpredictable behavior. table 11. register summary register name bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 main configuration 000 0 auxsel ifdiv 0 0 0 xin div2 lpwr 0 auto pdb 000 1 phase detector gain 00000000000 0 k pi k p2 k p1 2 powerdown00000000000 0 0 0 0 0 pdib pdrb 3rf1 n divider n rf1 4rf2 n divider 0n rf2 5 if n divider 0 0 n if 6rf1 r divider 000 0 0 r rf1 7rf2 r divider 000 0 0 r rf2 8 if r divider 0 0 0 0 0 r if 9 reserved . . . 15 reserved
si4136/si4126 22 rev. 1.4 register 0. main configuration address field = a[3:0] = 0000 bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 auxsel ifdiv 0 0 0 xin div2 lpwr 0 auto pdb 000 bit name function 17:14 reserved program to zero. 13:12 auxsel auxiliary output pin definition. 00 = reserved. 01 = force output low. 11 = lock detect (ldetb). 11:10 ifdiv if output divider 00 = ifout = ifvco frequency 01 = ifout= ifvco frequency/2 10 = ifout = ifvco frequency/4 11 = ifout = ifvco frequency/8 9:7 reserved program to zero. 6xindiv2 xin divide-by-2 mode. 0 = xin not divided by 2. 1 = xin divided by 2. 5lpwr output power-level settings for if synthesizer circuit. 0 = r load < 500 ? ?normal power mode. 1 = r load 500 ? ?low power mode. 4 reserved program to zero. 3 autopdb auto powerdown 0 = software powerdown is controlled by register 2. 1 = equivalent to setting all bits in register 2 = 1. 2:0 reserved program to zero.
si4136/si4126 rev. 1.4 23 register 1. phase detector gain address field (a[3:0]) = 0001 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 000000000000 k pi k p2 k p1 bit name function 17:6 reserved program to zero. 5:4 k pi if phase detector gain constant. n value k pi <2048 = 00 2048?4095 = 01 4096?8191 = 10 >8191 = 11 3:2 k p2 rf2 phase detector gain constant. n value k p2 <2048 = 00 2048?4095 = 01 4096?8191 = 10 >8191 = 11 1:0 k p1 rf1 phase detector gain constant. n value k p1 <4096 = 00 4096?8191 = 01 8192?16383 = 10 >16383 = 11
si4136/si4126 24 rev. 1.4 register 2. powerdown address field (a[3:0]) = 0010 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3 d2 d1 d0 name 000000000000000 0 pdib pdrb bit name function 17:2 reserved program to zero. 1pdib powerdown if synthesizer. 0 = if synthesizer powered down. 1 = if synthesizer on. 0 pdrb powerdown rf synthesizer. 0 = rf synthesizer powered down. 1 = rf synthesizer on. register 3. rf1 n divider address field (a[3:0]) = 0011 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name n rf1 bit name function 17:0 n rf1 n divider for rf1 synthesizer. n rf1 992. register 4. rf2 n divider address field = a[3:0] = 0100 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0n rf2 bit name function 17 reserved program to zero. 16:0 n rf2 n divider for rf2 synthesizer. n rf2 240.
si4136/si4126 rev. 1.4 25 register 5. if n divider address field (a[3:0]) = 0101 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00 n if bit name function 17:16 reserved program to zero. 15:0 n if n divider for if synthesizer. n if 56. register 6. rf1 r divider address field (a[3:0]) = 0110 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00000 r rf1 name function 17:13 reserved program to zero. 12:0 r rf1 r divider for rf1 synthesizer. r rf1 can be any value from 7 to 8189 if k p1 = 00 8 to 8189 if k p1 = 01 10 to 8189 if k p1 = 10 14 to 8189 if k p1 = 11 register 7. rf2 r divider address field (a[3:0]) = 0111 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00000 r rf2 bit name function 17:13 reserved program to zero. 12:0 r rf2 r divider for rf2 synthesizer. r rf2 can be any value from 7 to 8189 if k p2 = 00 8 to 8189 if k p2 = 01 10 to 8189 if k p2 = 10 14 to 8189 if k p2 = 11
si4136/si4126 26 rev. 1.4 register 8. if r divider address field (a[3:0]) = 1000 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00000 r if bit name function 17:13 reserved program to zero. 12:0 r if r divider for if synthesizer. r if can be any value from 7 to 8189 if k p1 = 00 8 to 8189 if k p1 = 01 10 to 8189 if k p1 = 10 14 to 8189 if k p1 = 11
si4136/si4126 rev. 1.4 27 4. pin descriptions: si4136-bt/gt pin number(s) name description 1 sclk serial clock input 2 sdata serial data input 3, 4, 6, 8?10, 16, 18, 21 gnd common ground 5, 7 nc no connect 11 rfout radio frequency (rf) output of the selected rf vco 12 vddr supply voltage for the rf analog circuitry 13 auxout auxiliary output 14 pwdn powerdown input pin 15 xin reference frequency amplifier input 17 vddd supply voltage for digital circuitry 19, 20 ifla, iflb pins for inductor connection to if vco 22 ifout intermediate frequency (if) output of the if vco 23 vddi supply voltage for if analog circuitry 24 sen enable serial port input sclk sdata gnd gnd nc gnd nc gnd gnd gnd rfout vddr sen vddi ifout gnd iflb ifla gnd vddd gnd xin pwdn auxout 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
si4136/si4126 28 rev. 1.4 5. pin descriptions: si4136-bm/gm pin number(s) name description 1, 2, 4, 6, 7?9, 14, 16, 18, 21, 22, 28 gnd common ground 3, 5 nc no connect 10 rfout radio frequency (rf) output of the selected rf vco 11 vddr supply voltage for the rf analog circuitry 12 auxout auxiliary output 13 pwdn powerdown input pin 15 xin reference frequency amplifier input 17 vddd supply voltage for digital circuitry 19, 20 ifla, iflb pins for indu ctor connection to if vco 23 ifout intermediate frequency (if) output of the if vco 24 vddi supply voltage for if analog circuitry 25 sen enable serial port input 26 sclk serial clock input 27 sdata serial data input sclk sdata gnd gnd nc nc gnd gnd rfout vddr sen vddi ifout gnd iflb ifla gnd vddd gnd xin pwdn auxout 21 20 19 18 17 16 15 8 9 10 11 12 13 14 28 27 26 25 24 23 22 1 2 3 4 5 6 7 gnd gnd gnd gnd gnd gnd gnd
si4136/si4126 rev. 1.4 29 6. ordering guide 7. si4136 deri vative devices the si4136 performs both if and dual-band rf frequency synt hesis. the si4126 is a derivative of this device. the si4126 features two synthesizers, rf2 and if; it does not include rf1. the pinouts for the si4126 and the si4136 are the same. unused registers related to rf1 should be programmed to zero. ordering part number description lead-free/ rohs compliant temperature si4136-f-bt 2.5 ghz/2.3 ghz/if out ?40 to 85 o c si4136-f-gt 2.5 ghz/2.3 ghz/if out/lead free d ?40 to 85 o c si4136-f-bm 2.5 ghz/2.3 ghz/if out ?40 to 85 o c si4136-f-gm 2.5 ghz/2.3 ghz/if out/lead free d ?40 to 85 o c si4126-f-bm 2.3 ghz/if out ?40 to 85 o c si4126-f-gm 2.3 ghz/if out/lead free d ?40 to 85 o c
si4136/si4126 30 rev. 1.4 8. package outl ine: si4136-bt/gt figure 18 illustrates the package details for the si4136-bt/gt. table 12 lists the values for the dimensions shown in the illustration. figure 18. 24-pin thin shrink small outline package (tssop) table 12. package diagram dimensions symbol millimeters min nom max a? ?1.20 a1 0.05 ? 0.15 b 0.19 ? 0.30 c 0.09 ? 0.20 d7.707.80 7.90 e 0.65 bsc e 6.40 bsc e1 4.30 4.40 4.50 l 0.450.600.75 0 ? 8 aaa 0.10 bbb 0.10 ccc 0.05 ddd 0.20 e1 e e d l c a a1 b e/2 bbb c b a m 2x ddd c b a a ccc 24x aaa c seating plane c
si4136/si4126 rev. 1.4 31 9. package outl ine: si4136-bm/gm figure 19 illustrates the package details for the si4136- bm/gm. table 13 lists the valu es for the dimensions shown in the illustration. figure 19. 28-pin quad flat no-lead (qfn) table 13. package dimensions controlling dimension: mm symbol millimeters min nom max a ? 0.85 0.90 a1 0.00 0.01 0.05 b 0.18 0.23 0.30 d, e 5.00 bsc d2, e2 2.55 2.70 2.85 n28 e 0.50 bsc l 0.50 0.60 0.75 12 e/2 e a n d/2 d a1 a b n e l bottom view top view 1 2 3 1 2 3 pin 1 id 0.20 r d2 e2 b 0.10 c a 2x 0.10 c b 2x c 0.05 c seating plane 0.10 c a b m side view
si4136/si4126 32 rev. 1.4 d ocument c hange l ist revision 1.3 to revision 1.4 si4136-bt change to si4136-bt/gt si4136-bm change to si4136-bm/gm
si4136/si4126 rev. 1.4 33 n otes :
si4136/si4126 34 rev. 1.4 c ontact i nformation silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: rfinfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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